The present invention relates to a time counting circuit for measuring such time as the pulse spacing of a pulse signal, to a sampling circuit for sampling a signal inputted from the outside and amplifying a differential voltage between the sampled signal and a reference potential, to a skew adjusting circuit for adjusting a skew between a plurality of clock pulse signals, and to a logic analyzing circuit for analyzing the logic of a signal.
There have been rising hopes for the use of time counting circuits for measuring such time as the pulse spacing of a pulse signal in the field of digital communication and the like. In recent years, it has become possible to mount a time counting circuit composed of a CMOS transistor in conjunction with other digital circuits on a single chip, which has accomplished a significant reduction in the cost of manufacturing semiconductor devices.
A time counting circuit which exhibits further stabilized operation with higher accuracy may also find extensive application in various fields including the modulation of FM signals and the demodulation of bus signals in an LSI. If a time counting circuit capable of measuring an extremely short time with accuracy and stability can be utilized for the demodulation of bus signals in an LSI, the number of buses in the LSI can be reduced significantly.
FIG. 21 shows an example of the structure of a conventional time counting circuit, in which are shown: a delay circuit ring 51; a row of holding circuits 54; an operating circuit 55; a counter 56a; and a counter-output holding circuit 56b. A pulse-signal input terminal receives a pulse signal to be measured and an operation-result output terminal outputs time data representing the pulse spacing of the inputted pulse signal to be measured.
The time counting circuit shown in FIG. 21 includes the delay circuit ring 51 composed of seven delay circuits each consisting of two inverters and one delay circuit consisting of three inverters (the eighth delay circuit in FIG. 21), which are connected in a ring configuration. Since the delay circuit ring 51 is composed of the odd number of (2.times.7+3=17) inverters, so-called oscillation is observed whereby one signal transition occurs after another as though seemingly moving along the delay circuit ring 51 with the passage of time, resulting in circulations around the delay circuit ring 51. Therefore, time can be measured by examining variations in the output voltages from the respective delay circuits.
The output signals from the respective delay circuits composing the delay circuit ring 51 are held in flip-flops (FFs) composing the row of holding circuits 54. When the pulse to be measured rises, it is outputted to the operating circuit 55. The counter 56a counts the number of circulations of signal transition around the delay circuit ring 51 and outputs the counted number of circulations to the operating circuit 55 via the counter-output holding circuit 56b. The operating circuit 55 converts signals outputted from the row of holding circuits 54 to numeric data, calculates the pulse spacing of the pulse signal to be measured, and outputs the operation result from an output terminal for operation result (see "Time-to-Digital Converter LSI" Technical Report of IEICE, ICD93-77 (1993-08)).
However, the conventional time counting circuit has the following disadvantages.
FIG. 22(a) is a graph showing the transitions of the output voltages from the respective delay circuits composing the delay circuit ring 51. In the drawing, the straight line 1 represents the transition of the output voltage from the 1st delay circuit. Likewise, the straight lines 2 to 7 represent the transitions of the output voltages from the 2nd to 7th delay circuits, respectively.
As will be understood from FIG. 22(a), to shift from VSS (the logic level "0") to VDD (the logic level "1"), the output voltage from each delay circuit requires a given period of time. This is because each delay circuit drives a load appearing at the input terminal of the subsequent delay circuit, i.e., an input capacitance. Therefore, the period of time required for shifting corresponds to a charging period during which the input terminal of the subsequent delay circuit is charged.
For example, when the output voltage from the 1st delay circuit initiates shifting from "0" to "1", the output voltage from the 2nd delay circuit initiates shifting from "0" to "1" after a given delay time. Subsequently, the 3rd delay circuit initiates shifting from "0" to "1" after a given delay time. In this manner, the output voltages from the individual delay circuits sequentially shift. It follows therefore that, at a given time in FIG. 22(a), output voltages from a plurality of delay circuits are shifting.
The operation of the flip-flops (FF) composing the row of holding circuits 54 are not in synchronization with the operation of the delay circuit ring 51. Hence, there may be cases where not only a voltage representing the so-called logic level "0" or "1" but also an intermediate voltage in the transition from "0" to "1" is inputted to the flip-flops. Since the flip-flop is a circuit for holding and outputting an input signal on either one of the logic levels "0" and "1", it changes the intermediate voltage to either one of the logic levels "0" and "1" and holds it. Accordingly, there is a range of input voltages in which an input signal may be held as either "0" or "1" in the flip-flop. The range of input voltages is termed an indefinite range.
It is assumed here that the pulse to be measured rises at the time T in FIG. 22(a). In this case, since each of the output voltage from the 1st delay circuit and the output voltage from the 2nd delay circuit is in the indefinite range, the 1st flip-flop has a probability A (0&lt;A&lt;1) of holding "0" and a probability B (0&lt;B&lt;1, B=1-A) of holding "1". The 2nd flip-flop has a probability C (0&lt;C&lt;1) of holding "0" and a probability D (0&lt;D&lt;1, D=1-C) of holding "1".
As long as a time counting circuit as shown in FIG. 21 is operating normally, the outputs from the 1st to 5th flip-flops sequentially change from "00000" to "10000" and from "10000" to "11000". At the time T, however, the 1st to 5th flip-flops have a probability A.times.D of outputting "01000". At this point, the operating circuit 55 cannot operate properly and produces an error, which phenomenon is termed a mishold in the row of holding circuits.
There are other cases where the transitions of the output voltages from the delay circuits become sluggish and the indefinite range is expanded under the influence of noise in a power-source voltage supplied to the delay circuits and flip-flops or the like. FIG. 22(b) is a graph showing the transitions of the output voltages from the individual delay circuits in such cases. It is assumed here that the pulse signal to be measured rises at the time Te in FIG. 22(b). In this case, since the output voltages from the 2nd to 5th delay circuits are in the indefinite range, the probability that the row of holding circuits incurs a mishold becomes higher and an error resulting from the mishold becomes larger than in the case of FIG. 22(a).
The conventional time counting circuit also has other disadvantages.
Since actual transistors manufactured in a semiconductor manufacturing process have varied performances, the respective threshold voltages of actual flip-flips vary as well.
FIG. 23(a) is a graph showing the transitions of the output voltages from the respective delay circuits composing the delay circuit ring 51. In the drawing, the straight line 1 represents the transition of the output voltage from the 1st delay circuit. Likewise, the straight lines 2 to 7 represent the transitions of the output voltages from the 2nd to 7th delay circuits. Each of the threshold voltages of the 1st and 3rd to 7th flip-flops is represented by Va, while the threshold voltage of the 2nd flip-flop is represented by Vb.
FIG. 23(b) is a graph showing changes in the time codes outputted from the respective flip-flops composing the row of holding circuits 54. In the drawing, the time interval (time code 1) between the time at which the output voltage from the 1st delay circuit reaches the threshold voltage Va of the 1st flip-flop and the time at which the output voltage from the 2nd delay circuit reaches the threshold voltage Vb of the 2nd flip-flop is represented by t1. On the other hand, the time interval (time code 2) between the time at which the output voltage from the 2nd delay circuit reaches the threshold voltage Vb of the 2nd flip-flop and the time at which the output voltage from the 3rd delay circuit reaches the threshold voltage Va of the 3rd flip-flop is represented by t2.
Since the threshold voltage Va of each of the 1st and 3rd flip-flops is different from the threshold voltage Vb of the 2nd flip-flop, the time interval t1 representing the time code 1 differs from the time interval t2 representing the time code 2. Consequently, the linearity of time data relative to real time deteriorates and the accuracy with which time is measured is lowered.